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HT6116-70 CMOS 2Kx8-Bit SRAM
Features
* *
* * *
Single 5V power supply Low power consumption - Operating: 400mW (Typ.) - Standby: 5W (Typ.) 70ns (Max.) high speed access time Power down by pin CS TTL compatible interface levels
* * * * *
Fully static operation Memory expansion by pin OE Common I/O using tri-state outputs Pin-compatible with standard 2Kx8 bits of EPROM/MASK ROM 24-pin DIP/SDIP/SOP package
General Description
The HT6116-70 is a 16384-bit static random access memory. It is organized with 2048 words of 8 bits in length, and operates with a single 5V power supply. The IC is built with a high performance CMOS 0.8m process in order to obtain a low standby current and high reliability. The IC contains six-transistor full CMOS memory cells and TTL compatible inputs and outputs, which are easily interface with common system bus structures. The Data bus of the HT6116-70 is designed as a tri-state type. The IC is in the standby mode if the CS pin is set to "high".
Pin Assignment
Block Diagram
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Pin Description
Pin No.
8~1, 23, 22, 19 9~11 13~17 12 18 20 21 24
Pin Name
A0~A7 A8, A9, A10 D0~D2 D3~D7 VSS CS OE WE VDD
I/O
I I/O I I I I I Address inputs
Description
Data inputs and outputs Negative power supply, usually connected to the ground Chip select signal pin When this signal is high, the chip is in the standby mode. The chip is in the active mode, if CS is low. Output enable signal pin Write enable signal pin Positive power supply
Absolute Maximum Ratings*
Supply Voltage ............................-0.3V to +7.0V Input Voltage................. VSS-0.3V to VDD+0.3V Storage Temperature...............-50C to +125C Operating Temperature.............-40C to +85C
*Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied and exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. Characteristics
Symbol
VDD ILI ILO
(Ta=25C)
Parameter
Operating Voltage Input Leakage Current Output Leakage Current
Test Conditions VDD
-- 5V 5V 5V
Conditions
-- VIN=0 to VDD VO=0 to VDD VIH=2.2V, VIL=0.8V In write mode, tWC=1s. VIH=2.2V, VIL=0.8V In read mode, tRC=1s. VIH=2.2V, VIL=0.8V (TTL Input) VIH=4.8V, VIL=0.2V (CMOS Input)
Min. Typ. Max.
4.5 -- -- -- -- -- -- 5.0 0.1 0.1 45 80 0.8 0.1 5.5 10 10 90 90 1.5 3
Unit
V
A A
mA mA mA
IDD
Operating Current 5V 5V
ISTB
Standby Current 5V
A
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Test Conditions VDD
5V 5V 5V 5V VOH=4.5V VOL=0.5V
Symbol
VIH VIL IOH IOL
Parameter
Conditions
--
Min. Typ. Max.
2.2 -0.3 -1.2 4.8 2 0.2 -6.2 14.5 5.3 0.8 -- --
Unit
V V mA mA
Input Voltage Output Source Current Output Sink Current
A.C. Test Conditions
Item
Input pulse high level Input pulse low level Input and output reference level Output load VIH=3V VIL=0V 1.5V See Figures below
Condition
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A.C. Characteristics
Read cycle
(VDD=5V10%, GND=0V, Ta=-40C to +85C)
Symbol
tRC tAA tACS tOE tOH tCLZ tOLZ tOHZ tCHZ
Parameter
Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Output Hold from Address Change Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Output Disable to Output in High-Z Chip Disable to Output in High-Z
Min.
70 -- -- -- 10 10 10 0 0
Typ.
36 35 35 12 12 -- -- -- --
Max.
-- 70 70 40 -- -- -- 30 30
Unit
ns ns ns ns ns ns ns ns ns
Note: 1. A read occurs during the overlap of a low CS and a high WE 2. tCHZ and tOHZ are specified by the time when data out is floating
Write cycle
(VDD=5V10%, GND=0V, Ta=-40C to +85C)
Symbol
tWC tDW tDH tAW tAS tWP tWR tCW tOW tOHZ tWHZ
Parameter
Write Cycle Time Data Set up Time Data Hold Time from Write Time Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Chip Selection to End of Write Output Active from End of Write Output Disable to Output in High-Z Write to Output in High-Z
Min.
70 20 5 50 20 25 5 35 5 0 0
Typ.
36 18 0 15 14 0 -- -- -- -- --
Max.
-- -- -- --
Unit
ns ns ns ns ns
-- -- -- -- 40 50
ns ns ns ns ns ns
Note: 1. A write cycle occurs during the overlap of a low CS and a low WE 2. OE may be both high and low in a write cycle 3. tAS is specified from CS or WE, whichever occurs last 4. tWP is an overlap time of a low CS and a low WE 5. tWR, tDW and tDH is specified from CS or WE, whichever occurs first 6. tWHZ is specified by the time when DATA OUT is floating, not defined by output level 7. When I/O pins are data output mode, don't force inverse signals to those pins
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Functional Description
The HT6116-70 is a 2Kx8 bit SRAM. When the CS pin of the chip is set to "low", data can be written in or read from eight data pins; otherwise, the chip is in the standby mode. During a write cycle, the data pins are defined as the input state by setting the WE pin to low. Data should be ready before the rising edge of the WE pin according to the timing of the writing cycle. While in the read cycle, the WE pin is set to high and the OE pin is set to low to define the data pins as the output state. All data pins are defined as a three-state type, controlled by the OE pin. In both cycles (namely, write and read cycles), the locations are defined by the address pins A0~A10. The following table illustrates the relations of WE, OE, CS and their corresponding mode.
CS
H L L L where
OE
X L H X
WE
X H H L
Mode
Standby Read Read Write
D0~D7
High-Z Dout High-Z Din
X stands for "don't care". H stands for high level L stands for low level.
Timing Diagrams
Read cycle
(1)
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Read cycle
(1, 2, 4)
Read cycle
(1, 3, 4)
Notes:
(1) WE is high during the Read cycle (2) Device is continuously enabled, CS=VIL (3) Address is valid prior to or coincident with the CS transition low. (4) OE=VIL (5) Transition is measured500mV from the steady state.
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Write cycle 1 (1)
Write cycle 2 (1, 6)
Notes:
(1) WE must be high during all address transitions. (2) A write occurs during the overlap (tWP) of a low CS and a low WE. (3) tWR is measured from the earlier of CS or WE going high to the end of the write cycle. (4) During this period, I/O pins are in the output state, so the input signals of the opposite phase to the outputs must not be applied. (5) If the CS low transition occurs simultaneously with the WE low transitions or after the WE transition, outputs remain in a high impedance state.
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(6) OE is continuously low (OE=VIL). (7) DOUT is at the same phase of the write data of this write cycle. (8) DOUT is the read data of the next address. (9) If CS is low during this period, I/O pins are in the output state; then the data input signals of the opposite phase to the outputs must not be applied to them. (10) Transition is measured 500mV from the steady state.
Data Rentention Characteristics
Symbol
VDR ICCDR tCDR tR
(Ta=-40C to +85C)
Parameter
VDD for Data Retention Data Retention Current
Conditions
CS VDD-0.2V VDD=3V, CS VDD-0.2V VIN VDD-0.2V or VIN 0.2V
Min. Max. Unit
2 -- 0 tRC* 5.5 50 -- -- V
A
ns ns
Chip Disable Data Retention Time See Retention Timing Operation Recovery Time See Retention Timing
*tRC=Read Cycle Time
Low VDD Data Retention Timing
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Characteristic Curves
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